Formal verification is difficult to integrate with a real software development process. It takes time, the abstraction of Boolean logic are difficult to learn and the specifications are out of date as soon as the system is updated. But formal logic can be used to make my operation tasks easier and more efficient if instead of using booleans to prove systems correct you use them to reason about system behavior and test hypothesis.
An intro to different ways of applying the same techniques used in formal verification to improve testing, monitoring, and designing of systems
Engineers who are curious about verification but find the learning curve intimidating